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NLSX4373 2-Bit 20 Mb/s Dual-Supply Level Translator
The NLSX4373 is a 2-bit configurable dual-supply bidirectional auto sensing translator that does not require a directional control pin. The VCC I/O and VL I/O ports are designed to track two different power supply rails, VCC and VL respectively. The VCC supply rail is configurable from 1.5 V to 5.5 V while VL supply rail is configurable to 1.5 V to 5.5 V. This allows voltage logic signals on the VL side to be translated into lower, higher or equal value voltage logic signals on the VCC side, and vice-versa. The NLSX4373 translator has open-drain outputs with integrated 10 kW pullup resistors on the I/O lines. The integrated pullup resistors are used to pullup the I/O lines to either VL or VCC. The NLSX4373 is an excellent match for open-drain applications such as the I2C communication bus.
Features http://onsemi.com MARKING DIAGRAMS
8 1 UDFN8 MU SUFFIX CASE 517AJ VF = Specific Device Code M = Date Code G = Pb-Free Package 8 8 1 A L Y W G SO-8 D SUFFIX CASE 751 SX4373 ALYW G G 1 VFM G
* VL can be Less than, Greater than or Equal to VCC * Wide VCC Operating Range: 1.5 V to 5.5 V * * * * * * *
Wide VL Operating Range: 1.5 V to 5.5 V High-Speed with 20 Mb/s Guaranteed Date Rate Low Bit-to-Bit Skew Enable Input and I/O Lines have Overvoltage Tolerant (OVT) to 5.5 V Nonpreferential Powerup Sequencing Integrated 10 kW Pullup Resistors Small packaging: UDFN8, SO-8, Micro8 This is a Pb-Free Device
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package 8 Micro8 DM SUFFIX CASE 846A 1 4373 AYW G G
1 A Y W G
Typical Applications
* I2C, SMBus, PMBus * Low Voltage ASIC Level Translation * Mobile Phones, PDAs, Cameras
Important Information
= Assembly Location = Year = Work Week = Pb-Free Package
* ESD Protection for All Pins
ORDERING INFORMATION
Device NLSX4373MUTAG NLSX4373DR2G NLSX4373DMR2G Package Shipping UDFN8 3000/T ape & Reel (Pb-Free) SO-8 2500/T ape & Reel (Pb-Free) Micro8 4000/T ape & Reel (Pb-Free)
- Human Body Model (HBM) > 7000 V
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2009
December, 2009 - Rev. 3
1
Publication Order Number: NLSX4373/D
NLSX4373
LOGIC DIAGRAM
EN VL VCC GND
I/O VL1
I/O VCC1
I/O VL2
I/O VCC2
PIN ASSIGNMENTS
VL I/O VL1 I/O VL2 GND 1 2 3 4 UDFN8 (Top View) 8 7 6 5 VCC I/O VCC1 I/O VCC2 EN VL 1 I/O VL1 2 I/O VL2 3 GND 4 SOIC-8 (Top View) 8 7 6 5 VCC I/O VCC1 I/O VCC2 EN VL I/O VL1 I/O VL2 GND 1 2 3 4 Micro8 (Top View) 8 7 6 5 VCC I/O VCC1 I/O VCC2 EN
PIN ASSIGNMENT
Pins VCC VL GND EN I/O VCCn I/O VLn Description VCC Input Voltage VL Input Voltage Ground Output Enable VCC I/O Port, Referenced to VCC VL I/O Port, Referenced to VL
FUNCTION TABLE
EN L H Operating Mode Hi-Z I/O Buses Connected
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NLSX4373
MAXIMUM RATINGS
Symbol VCC VL I/O VCC I/O VL VEN II/O_SC TSTG Parameter High-side DC Supply Voltage High-side DC Supply Voltage VCC-Referenced DC Input/Output Voltage VL-Referenced DC Input/Output Voltage Enable Control Pin DC Input Voltage Short-Circuit Duration (I/O VL and I/O VCC to GND) Storage Temperature Value -0.3 to +7.0 -0.3 to +7.0 -0.3 to (VCC + 0.3) -0.3 to (VL + 0.3) -0.3 to +7.0 40 -65 to +150 Continuous Condition Unit V V V V V mA C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VL VEN VIO TA Parameter High-side Positive DC Supply Voltage High-side Positive DC Supply Voltage Enable Control Pin Voltage Enable Control Pin Voltage Operating Temperature Range VL Min 1.5 1.5 GND GND -40 VCC Max 5.5 5.5 5.5 5.5 +85 Unit V V V V C
PU1
One-Shot Block Gate Bias
One-Shot Block
PU2
RPullup 10 kW
RPullup 10 kW
I/O VL
N
I/O VCC
Figure 1. Block Diagram (1 I/O Line)
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NLSX4373
DC ELECTRICAL CHARACTERISTICS (VCC = 1.5 V to 5.5 V and VL = 1.5 V to 5.5 V, unless otherwise specified)
-405C to +855C Symbol VIHC VILC VIHL VILL VIH VIL VOHC VOLC VOHL VOLL IQVCC IQVL ITS-VCC ITS-VL IOZ RPU Parameter I/O VCC Input HIGH Voltage I/O VCC Input LOW Voltage I/O VL Input HIGH Voltage I/O VL Input LOW Voltage Control Pin Input HIGH Voltage Control Pin Input LOW Voltage I/O VCC Output HIGH Voltage I/O VCC Output LOW Voltage I/O VL Output HIGH Voltage I/O VL Output LOW Voltage VCC Supply Current VL Supply Current VCC Tristate Output Mode Supply Current VL Tristate Output Mode Supply Current I/O Tristate Output Mode Leakage Current Pullup Resistor I/O VL and VCC I/O VCC Source Current = 20 mA I/O VCC Sink Current = 20 mA I/O VL Source Current = 20 mA I/O VL Sink Current = 20 mA I/O VCC and I/O VL Unconnected, VEN = VL I/O VCC and I/O VL Unconnected, VEN = VL I/O VCC and I/O VL Unconnected, VEN = GND I/O VCC and I/O VL Unconnected, VEN = GND TA = +25C TA = +25C Test Conditions Min VCC - 0.4 - VL - 0.2 - VL - 0.2 - 2/3 * VCC - 2/3 * VL - - - - - - - Typ (Notes 1, 2) - - - - - - - - - - 0.5 0.3 0.1 0.1 0.1 10 Max - 0.15 - 0.15 - 0.15 - 1/3 * VCC - 1/3 * VL 2.0 1.5 1.0 1.0 1.0 - Unit V V V V V V V V V V mA mA mA mA mA kW
1. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25C. 2. All units are production tested at TA = +25C. Limits over the operating temperature range are guaranteed by design.
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NLSX4373
TIMING CHARACTERISTICS - RAIL-TO-RAIL DRIVING CONFIGURATIONS
(I/O test circuit of Figures 2 and 3, CLOAD = 15 pF, driver output impedance v 50 W, RLOAD = 1 MW) -405C to +855C (Notes 3 and 4) Symbol VL = 1.5 V, VCC = 5.5 V tRVCC tFVCC tRVL tFVL tPDVL-VCC tPDVCC-VL tPPSKEW I/O VCC Risetime I/O VCC Falltime I/O VL Risetime I/O VL Falltime Propagation Delay (Driving I/O VL) Propagation Delay (Driving I/O VCC) Part-to-Part Skew Maximum Data Rate VL = 1.8 V, VCC = 2.8 V tRVCC tFVCC tRVL tFVL tPDVL-VCC tPDVCC-VL tPPSKEW I/O VCC Risetime I/O VCC Falltime I/O VL Risetime I/O VL Falltime Propagation Delay (Driving I/O VL) Propagation Delay (Driving I/O VCC) Part-to-Part Skew Maximum Data Rate VL = 2.5 V, VCC = 3.6 V tRVCC tFVCC tRVL tFVL tPDVL-VCC tPDVCC-VL tPPSKEW I/O VCC Risetime I/O VCC Falltime I/O VL Risetime I/O VL Falltime Propagation Delay (Driving I/O VL) Propagation Delay (Driving I/O VCC) Part-to-Part Skew Maximum Data Rate VL = 2.8 V, VCC = 1.8 V tRVCC tFVCC tRVL tFVL tPDVL-VCC tPDVCC-VL tPPSKEW I/O VCC Risetime I/O VCC Falltime I/O VL Risetime I/O VL Falltime Propagation Delay (Driving I/O VL) Propagation Delay (Driving I/O VCC) Part-to-Part Skew Maximum Data Rate 20 25 10 20 15 15 15 5 ns ns ns ns ns ns nS Mb/s 20 15 10 15 10 15 15 5 ns ns ns ns ns ns nS Mb/s 20 15 15 25 10 15 15 5 ns ns ns ns ns ns nS Mb/s 20 15 20 30 10 20 20 5 ns ns ns ns ns ns nS Mb/s Parameter Test Conditions Min Typ Max Unit
3. Typical values are for VCC = +3.3 V, VL = +1.8 V and TA = +25C. 4. All units are production tested at TA = +25C. Limits over the operating temperature range are guaranteed by design.
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NLSX4373
TIMING CHARACTERISTICS - RAIL-TO-RAIL DRIVING CONFIGURATIONS
(I/O test circuit of Figures 2 and 3, CLOAD = 15 pF, driver output impedance v 50 W, RLOAD = 1 MW) -405C to +855C (Notes 3 and 4) Symbol VL = 3.6 V, VCC = 2.5 V tRVCC tFVCC tRVL tFVL tPDVL-VCC tPDVCC-VL tPPSKEW I/O VCC Risetime I/O VCC Falltime I/O VL Risetime I/O VL Falltime Propagation Delay (Driving I/O VL) Propagation Delay (Driving I/O VCC) Part-to-Part Skew Maximum Data Rate VL = 5.5 V, VCC = 1.5 V tRVCC tFVCC tRVL tFVL tPDVL-VCC tPDVCC-VL tPPSKEW I/O VCC Risetime I/O VCC Falltime I/O VL Risetime I/O VL Falltime Propagation Delay (Driving I/O VL) Propagation Delay (Driving I/O VCC) Part-to-Part Skew Maximum Data Rate 20 30 10 15 20 20 20 5 ns ns ns ns ns ns nS Mb/s 20 15 10 15 15 15 15 5 ns ns ns ns ns ns nS Mb/s Parameter Test Conditions Min Typ Max Unit
3. Typical values are for VCC = +3.3 V, VL = +1.8 V and TA = +25C. 4. All units are production tested at TA = +25C. Limits over the operating temperature range are guaranteed by design.
TIMING CHARACTERISTICS - OPEN DRAIN DRIVING CONFIGURATIONS
(I/O test circuit of Figures 4 and 5, CLOAD = 15 pF, driver output impedance v 50 W, RLOAD = 1 MW) -405C to +855C (Notes 5 and 6) Symbol +1.5 v VL v VCC v +5.5 V tRVCC tFVCC tRVL tFVL tPDVL-VCC tPDVCC-VL tPPSKEW MDR I/O VCC Risetime I/O VCC Falltime I/O VL Risetime I/O VL Falltime Propagation Delay (Driving I/O VL) Propagation Delay (Driving I/O VCC) Part-to-Part Skew Maximum Data Rate 2 400 50 400 60 1000 1000 50 ns ns ns ns ns ns nS Mb/s Parameter Test Conditions Min Typ Max Unit
5. Typical values are for VCC = +3.3 V, VL = +1.8 V and TA = +25C. 6. All units are production tested at TA = +25C. Limits over the operating temperature range are guaranteed by design.
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NLSX4373
TEST SETUPS
VL EN Source I/O VL
NLSX4373
VCC I/O VCC CLOAD RLOAD I/O VL
VL EN
NLSX4373
VCC I/O VCC
CLOAD RLOAD Source
Figure 2. Rail-to-Rail Driving I/O VL
Figure 3. Rail-to-Rail Driving I/O VCC
VL EN I/O VL
NLSX4373
VCC I/O VCC CLOAD RLOAD
VL EN VCC CLOAD RLOAD
NLSX4373
VCC I/O VCC
Figure 4. Open-Drain Driving I/O VL
Figure 5. Open-Drain Driving I/O VCC
I/O VL 90% 50% 10% tPD_VL-VCC I/O VCC 90% 50% 10%
tRISE/FALL v 3 ns
I/O VCC 90% 50% 10% tPD_VL-VCC tPD_VCC-VL I/O VL 90% 50% 10%
tRISE/FALL v 3 ns
tPD_VCC-VL
tF-VCC
tR-VCC
tF-VL
tR-VL
Figure 6. Definition of Timing Specification Parameters
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NLSX4373
VCC R1 CL RL 2xVCC OPEN
PULSE GENERATOR RT
DUT
Test tPZH, tPHZ tPZL, tPLZ
Switch Open 2 x VCC
CL = 15 pF or equivalent (Includes jig and probe capacitance) RL = R1 = 50 kW or equivalent RT = ZOUT of pulse generator (typically 50 W)
Figure 7. Test Circuit for Enable/Disable Time Measurement
tR Input tPLH Output 90% 50% 10% 90% 50% 10% tR tPHL tF 50% VL GND HIGH IMPEDANCE 10% 90% VOL VOH HIGH IMPEDANCE
VCC GND
EN
tPZL Output 50% tPZH Output 50%
tPLZ
tF
tPHZ
Figure 8. Timing Definitions for Propagation Delays and Enable/Disable Measurement
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NLSX4373
APPLICATIONS INFORMATION
Level Translator Architecture
The NLSX4373 auto sense translator provides bi-directional voltage level shifting to transfer data in multiple supply voltage systems. This device has two supply voltages, VL and VCC, which set the logic levels on the input and output sides of the translator. When used to transfer data from the VL to the VCC ports, input signals referenced to the VL supply are translated to output signals with a logic level matched to VCC. In a similar manner, the VCC to VL translation shifts input signals with a logic level compatible to VCC to an output signal matched to VL. The NLSX4373 consists of two bi-directional channels that independently determine the direction of the data flow without requiring a directional pin. The one-shot circuits are used to detect the rising or falling input signals. In addition, the one shots decrease the rise and fall time of the output signal for high-to-low and low-to-high transitions. Each input/output channel has an internal 10 kW pull. The magnitude of the pullup resistors can be reduced by connecting external resistors in parallel to the internal 10 kW resistors.
Input Driver Requirements
parameters listed in the data sheet assume that the output impedance of the drivers connected to the translator is less than 50 kW.
Enable Input (EN)
The NLSX4373 has an Enable pin (EN) that provides tri-state operation at the I/O pins. Driving the Enable pin to a low logic level minimizes the power consumption of the device and drives the I/O VCC and I/O VL pins to a high impedance state. Normal translation operation occurs when the EN pin is equal to a logic high signal. The EN pin is referenced to the VL supply and has Overvoltage Tolerant (OVT) protection.
Power Supply Guidelines
The rise (tR) and fall (tF) timing parameters of the open drain outputs depend on the magnitude of the pull-up resistors. In addition, the propagation times (tPD), skew (tPSKEW) and maximum data rate depend on the impedance of the device that is connected to the translator. The timing
During normal operation, supply voltage VL can be greater than, less than or equal to VCC. The sequencing of the power supplies will not damage the device during the power up operation. For optimal performance, 0.01 mF to 0.1 mF decoupling capacitors should be used on the VL and VCC power supply pins. Ceramic capacitors are a good design choice to filter and bypass any noise signals on the voltage lines to the ground plane of the PCB. The noise immunity will be maximized by placing the capacitors as close as possible to the supply and ground pins, along with minimizing the PCB connection traces.
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NLSX4373
PACKAGE DIMENSIONS
UDFN8 1.8 x 1.2, 0.4P CASE 517AJ-01 ISSUE O
D 0.10 C
PIN ONE REFERENCE
AB L1 DETAIL A
NOTE 5
E
0.10 C
TOP VIEW (A3) A
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP. 4. MOLD FLASH ALLOWED ON TERMINALS ALONG EDGE OF PACKAGE. FLASH MAY NOT EXCEED 0.03 ONTO BOTTOM SURFACE OF TERMINALS. 5. DETAIL A SHOWS OPTIONAL CONSTRUCTION FOR TERMINALS. DIM A A1 A3 b b2 D E e L L1 L2 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.127 REF 0.15 0.25 0.30 REF 1.80 BSC 1.20 BSC 0.40 BSC 0.45 0.55 0.00 0.03 0.40 REF
0.05 C 0.05 C
e/2 (b2)
1 4
(L2)
8 5 8X b
BOTTOM VIEW
II II
SIDE VIEW
A1
C
SEATING PLANE
e
DETAIL A 8X
L
MOUNTING FOOTPRINT SOLDERMASK DEFINED
0.10 0.05
M M
CAB C
NOTE 3
0.22
7X
0.66
8X
1.50 1 0.32 0.40 PITCH
DIMENSIONS: MILLIMETERS
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NLSX4373
PACKAGE DIMENSIONS
SO-8 CASE 751-07 ISSUE AJ
-X- A
8 5
B
1
S
4
0.25 (0.010)
M
Y
M
-Y- G
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
C -Z- H D 0.25 (0.010)
M SEATING PLANE
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NLSX4373
PACKAGE DIMENSIONS
Micro8t CASE 846A-02 ISSUE H
D
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846A-01 OBSOLETE, NEW STANDARD 846A-02. MILLIMETERS INCHES DIM MIN NOM MAX MIN NOM MAX A -- -- 1.10 -- -- 0.043 A1 0.05 0.08 0.15 0.002 0.003 0.006 b 0.25 0.33 0.40 0.010 0.013 0.016 c 0.13 0.18 0.23 0.005 0.007 0.009 D 2.90 3.00 3.10 0.114 0.118 0.122 E 2.90 3.00 3.10 0.114 0.118 0.122 e 0.65 BSC 0.026 BSC L 0.40 0.55 0.70 0.016 0.021 0.028 HE 4.75 4.90 5.05 0.187 0.193 0.199
HE
E
PIN 1 ID
e
b 8 PL 0.08 (0.003)
M
TB
S
A
S
-T- PLANE 0.038 (0.0015) A1
SEATING
A c L
SOLDERING FOOTPRINT*
8X
1.04 0.041
0.38 0.015
8X
3.20 0.126
4.24 0.167
5.28 0.208
6X
0.65 0.0256
SCALE 8:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NLSX4373/D

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